Migrating from UltraScale+ Devices to Versal Adaptive SoCs

This guide provides a comprehensive course specification for migrating existing designs from AMD UltraScale+ devices to the AMD Versal adaptive SoCs. It outlines various methodologies for system design planning and partitioning, emphasizing the identification and comparison of functional blocks between the two device generations. The course covers essential topics such as design migration considerations for different system types, enabling top-level RTL flows, and specific guidelines for PL-only and Zynq UltraScale+ MPSoC designs. It also details the architecture overview for existing users, system design migration approaches, and the programming model for AI Engines. The course is designed for software and hardware developers, system architects, and others involved in the migration process, requiring familiarity with UltraScale+ FPGAs and AMD development tools. The document includes updated features for the latest software versions and highlights the necessary skills participants will gain upon completion.