CXL 2.0 Specification and Pre-Silicon Simulation Case Study

This white paper discusses the Compute Express Link™ (CXL™) 2.0 specification and its role in enhancing high-bandwidth applications, particularly in artificial intelligence and machine learning. It outlines the challenges and strategies involved in achieving interoperability (interop) between Intel hosts and Cadence IP through pre-silicon simulation. The document details the verification challenges faced in the development of CXL 2.0, emphasizing the importance of early interop testing to ensure compatibility and performance. It describes the collaborative efforts between Cadence and Intel to test the CXL 2.0 Controller IP, highlighting the need for backward compatibility with CXL 1.1. The paper also presents the logistics of CXL simulation, including the support for various operational modes and the establishment of a joint test plan to assess success metrics. The findings indicate that pre-silicon RTL interop significantly enhances design quality and accelerates the verification process, providing valuable insights for the wider developer community.