Design Space Exploration of Processing-near-Bank Architectures

This technical report presents a novel framework for exploring Compute-near-Memory (CnM) architectures that interface with DRAM memory banks. The report outlines the challenges and trade-offs associated with near-DRAM computing strategies, particularly in addressing the memory-to-processor communication bottleneck. It details the methodology employed to analyze the architectural configurations, focusing on performance, energy, and area metrics. Two studies are exemplified: one analyzing the interaction between control and data resources, and another exploring the integration of processing units with various DRAM standards. The findings indicate that optimal size ratios between instruction and data capacity range from 2× to 4× across different benchmarks. Additionally, the report documents the performance improvements achieved with the proposed framework, including a 50% increase in performance for matrix operations with a 15% energy overhead compared to existing designs. The framework also allows for the systematic exploration of architectural parameters and their impact on performance, energy consumption, and area.