FPGA-based Object Detection Accelerator Architecture

This technical report presents an FPGA-based architecture designed for object detection, emphasizing multi-channel parallel computation to enhance performance in resource-constrained environments such as Unmanned Aerial Vehicles (UAVs) and Unmanned Surface Vehicles (USVs). The architecture accelerates computationally intensive modules including convolution, pooling, and upsampling layers through hardware, while utilizing an embedded CPU for other functions. Key design methodologies such as pipeline design, loop expansion, and data reordering are employed to optimize hardware acceleration modules. A data transmission architecture is introduced, featuring multi-channel transmission and ping-pong buffering to minimize data access delays. The tiny-YOLOv4 model is implemented as a hardware accelerator, integrating convolutional layers with normalization and various attention mechanisms to improve feature extraction and reduce computational load. Experimental validation demonstrates the accelerator's efficiency, consuming only 2.4W while outperforming existing solutions, making it suitable for integration into intelligent transportation systems and other complex applications.