FORC: High-Throughput FPGA Accelerator for ORC Files

This document is a technical report that presents FORC, a high-throughput streaming FPGA accelerator designed for decoding Apache ORC (Optimized Row Columnar) files utilized in big data engines. The report outlines the challenges associated with the computation bottleneck on CPUs when decompressing and decoding ORC files, particularly in the context of high-bandwidth SSDs. It details the architecture of FORC, which integrates a resource-efficient overlay design and a fully pipelined decoder engine capable of processing up to four 512-bit wide streaming writes per cycle. The document provides experimental results demonstrating that FORC achieves a decoding throughput of up to 12.9GB/s on an AMD/Xilinx Alveo U280 FPGA, significantly outperforming traditional CPU implementations. Additionally, it discusses the end-to-end dataflow integration of the accelerator with the Apache ORC C++ library, emphasizing its efficiency in overlapping I/O read, CPU-FPGA data transfer, and FPGA computation. The report concludes with a description of the ORC file format and its encoding schemes, which are crucial for understanding the decoding process.