High-Throughput Lossless Compression on CPU-FPGA Platforms

This technical report presents a novel architecture for high-throughput lossless compression on tightly coupled CPU-FPGA platforms, specifically targeting modern Intel-Altera HARPv2 systems. The report outlines the challenges faced in achieving efficient data compression, particularly in the context of big data workloads, where traditional single-engine FPGA designs encounter bottlenecks that limit throughput and efficiency. The proposed multi-way parallel and fully pipelined architecture aims to enhance scalability and throughput without compromising clock frequency. Key innovations include a better data feeding method and a hash chain to optimize compression ratios. The architecture is shown to achieve a peak throughput of 12.8 GB/s, significantly surpassing existing designs. Furthermore, the report discusses the integration of the accelerator with CPU-FPGA communication, achieving practical end-to-end throughput rates of up to 10.0 GB/s. The findings indicate that the proposed design is suitable for real-world applications and could be beneficial for the community when open-sourced.