Cisco Enhances ASIC Observability with Synopsys SLM IPs

This case study outlines Cisco's integration of Synopsys Silicon Lifecycle Management (SLM) IPs into its Silicon One ASICs to enhance performance and reliability. With increasing complexity in SoC designs, Cisco faced challenges such as transistor aging due to temperature and voltage fluctuations, timing degradation, and inconsistent performance caused by on-chip process variations. To address these issues, Cisco deployed a suite of SLM IPs, including Process, Voltage and Temperature Monitors, Path Margin Monitors, and Clock Delay Monitors. These tools enable real-time monitoring of critical parameters, allowing for dynamic optimization of performance and power. The implementation has resulted in enhanced observability, improved reliability, and data-driven design optimization. Cisco is now leveraging SLM analytics tools to refine pre-silicon models and further optimize ASIC performance for advanced networking applications. This strategic deployment exemplifies Cisco's commitment to maintaining high standards in silicon technology.