Machine Learning Macro Placement for Chip Floorplanning

This white paper discusses the challenges and advancements in chip floorplanning, focusing specifically on macro placement using machine learning (ML) techniques. It outlines the complexity of modern chip designs, which often include billions of transistors and require careful consideration of power, performance, area, and congestion (PPAC) targets. The document explains that traditional floorplanning methods are becoming increasingly tedious and time-consuming, particularly for large designs. To address these challenges, the paper introduces ML-based automation as a solution that can significantly enhance the floorplanning process. By leveraging ML, designers can conduct rapid 'what-if' experiments to explore various placement options, leading to improved design outcomes. The paper also details how Synopsys' ML Macro Placement technology automates the macro placement process, optimizing for PPAC goals while reducing the need for manual iterations. The results demonstrate that this approach can lead to better timing, reduced power consumption, and fewer engineering change orders, ultimately accelerating the design process.